COE "testsub.coe"
VHDL "ROM_blank.vhd", "testsub.vhd", "testsub"

; pBlazIDE syntax to define an input port
; input_port_name DSIN <port_id#>[, “<input_file_name>”]
;
switches DSIN $00, "swin.txt"
readport DSIN $1F
; pBlazIDE syntax to define a write-only output port
; output_port_name DSOUT <port_id#>[, “<output_file_name>”]
;
LEDs DSOUT $01, "output_values.txt"
writeport DSOUT $1E

start: 
                    LOAD      s0, $27
                    LOAD      s1, 1
                    SUB       s0, $35
                    SUBC      s1, 1
                    STORE     s0, $01
                    STORE     s1, $02
                    OUT       s1, LEDs
                    
                    LOAD      s0, s0
                    LOAD      s1, s1

                    LOAD      s0, $28
                    LOAD      s1, 0
                    SUB       s0, $35
                    SUBC      s1, 1
                    STORE     s0, $04
                    STORE     s1, $05
                    OUT       s1, LEDs

                    LOAD      s0, s0
                    LOAD      s1, s1
loop:
                    IN        s0, switches
                    IN        s1, switches
                    SUB       s0, s1
                    SUBC      s1, 1
                    STORE     s0, $07
                    STORE     s1, $08
                    OUT       s1, LEDs
                    JUMP       loop

halt: 
                    JUMP      halt