| Property | Value |
| Project Name: | c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clock |
| Target Device: | xc3s200 |
| Report Generated: | Thursday 04/14/05 at 14:51 |
| Printable Summary (View as HTML) | uart_clock_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 143 | 3,840 | 3% | |
| Number of 4 input LUTs: | 159 | 3,840 | 4% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 155 | 1,920 | 8% | |
| Number of Slices containing only related logic: | 155 | 155 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 155 | 0% | |
| Total Number 4 input LUTs: | 276 | 3,840 | 7% | |
| Number used as logic: | 159 | |||
| Number used as a route-thru: | 13 | |||
| Number used for Dual Port RAMs: | 16 | |||
| Number used for 32x1 RAMs: | 52 | |||
| Number used as Shift registers: | 36 | |||
| Number of bonded IOBs: | 6 | 173 | 3% | |
| Number of Block RAMs: | 1 | 12 | 8% | |
| Number of GCLKs: | 2 | 8 | 25% | |
| Number of DCMs: | 1 | 4 | 25% |
| Property | Value |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| No Constraints Found |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Thursday 04/14/05 at 14:51 |
| Translation Report | Current | Thursday 04/14/05 at 14:51 |
| Map Report | Current | Thursday 04/14/05 at 14:51 |
| Pad Report | Current | Thursday 04/14/05 at 14:51 |
| Place and Route Report | Current | Thursday 04/14/05 at 14:51 |
| Post Place and Route Static Timing Report | Current | Thursday 04/14/05 at 14:51 |
| Bitgen Report | Current | Thursday 04/14/05 at 14:51 |