-- -- KCPSM3 reference design - Real Time Clock with UART communications -- -- Ken Chapman - Xilinx Ltd - October 2003 -- -- The design demonstrates the following:- -- Connection of KCPSM3 to Program ROM -- Connection of UART macros supplied with PicoBlaze with -- Baud rate generation -- Definition of input and output ports with -- Minimum decoding -- Pipelining where appropriate -- Interrupt circuit with -- Simple fixed period timer -- Automatic clearing using interrupt acknowledge from KCPSM3 -- -- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud. -- Please read design documentation to modify to your own requirements. -- ------------------------------------------------------------------------------------ -- -- NOTICE: -- -- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other -- third parties. By providing this core as one possible implementation of a standard, -- Xilinx is making no representation that the provided implementation of this standard -- is free from any claims of infringement by any third party. Xilinx expressly -- disclaims any warranty with respect to the adequacy of the implementation, including -- but not limited to any warranty or representation that the implementation is free -- from claims of any third party. Furthermore, Xilinx is providing this core as a -- courtesy to you and suggests that you contact all third parties to obtain the -- necessary rights to use this implementation. -- ------------------------------------------------------------------------------------ -- -- Library declarations -- -- Standard IEEE libraries -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- -- Xilinx primitives -- Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------------ -- -- entity uart_clock is Port ( tx : out std_logic; rx : in std_logic; alarm : out std_logic; clk : in std_logic; -- DCM signals rst : in std_logic; LED1 : out std_logic ); end uart_clock; -- ------------------------------------------------------------------------------------ -- -- Start of test architecture -- architecture Behavioral of uart_clock is -- ------------------------------------------------------------------------------------ -- -- declaration of KCPSM3 -- component kcpsm3 Port ( address : out std_logic_vector(9 downto 0); instruction : in std_logic_vector(17 downto 0); port_id : out std_logic_vector(7 downto 0); write_strobe : out std_logic; out_port : out std_logic_vector(7 downto 0); read_strobe : out std_logic; in_port : in std_logic_vector(7 downto 0); interrupt : in std_logic; interrupt_ack : out std_logic; reset : in std_logic; clk : in std_logic); end component; -- -- declaration of program ROM -- component uclock Port ( address : in std_logic_vector(9 downto 0); instruction : out std_logic_vector(17 downto 0); clk : in std_logic); end component; -- -- declaration of UART transmitter with integral 16 byte FIFO buffer -- component uart_tx Port ( data_in : in std_logic_vector(7 downto 0); write_buffer : in std_logic; reset_buffer : in std_logic; en_16_x_baud : in std_logic; serial_out : out std_logic; buffer_full : out std_logic; buffer_half_full : out std_logic; clk : in std_logic); end component; -- -- declaration of UART Receiver with integral 16 byte FIFO buffer -- component uart_rx Port ( serial_in : in std_logic; data_out : out std_logic_vector(7 downto 0); read_buffer : in std_logic; reset_buffer : in std_logic; en_16_x_baud : in std_logic; buffer_data_present : out std_logic; buffer_full : out std_logic; buffer_half_full : out std_logic; clk : in std_logic); end component; -- -- COMPONENT ClockGen PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; -- ------------------------------------------------------------------------------------ -- -- Signals used to connect KCPSM3 to program ROM and I/O logic -- signal address : std_logic_vector(9 downto 0); signal instruction : std_logic_vector(17 downto 0); signal port_id : std_logic_vector(7 downto 0); signal out_port : std_logic_vector(7 downto 0); signal in_port : std_logic_vector(7 downto 0); signal write_strobe : std_logic; signal read_strobe : std_logic; signal interrupt : std_logic; signal interrupt_ack : std_logic; -- -- Signals for connection of peripherals -- signal uart_status_port : std_logic_vector(7 downto 0); -- -- Signals to form an timer generating an interrupt every microsecond -- signal timer_count : integer range 0 to 63 :=0; signal timer_pulse : std_logic; -- -- Signals for UART connections -- signal baud_count : integer range 0 to 127 :=0; signal en_16_x_baud : std_logic; signal write_to_uart : std_logic; signal tx_full : std_logic; signal tx_half_full : std_logic; signal read_from_uart : std_logic; signal rx_data : std_logic_vector(7 downto 0); signal rx_data_present : std_logic; signal rx_full : std_logic; signal rx_half_full : std_logic; -- -- Signals for DCM -- signal clk55MHz : std_logic; -- 55 MHz clock generated from DCM signal clk_in : std_logic; -- buffered 50 MHz input clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -- -- Start of circuit description -- begin -- ---------------------------------------------------------------------------------------------------------------------------------- -- KCPSM3 and the program memory ---------------------------------------------------------------------------------------------------------------------------------- -- processor: kcpsm3 port map( address => address, instruction => instruction, port_id => port_id, write_strobe => write_strobe, out_port => out_port, read_strobe => read_strobe, in_port => in_port, interrupt => interrupt, interrupt_ack => interrupt_ack, reset => '0', clk => clk55MHz); program_rom: uclock port map( address => address, instruction => instruction, clk => clk55MHz); -- ---------------------------------------------------------------------------------------------------------------------------------- -- Interrupt ---------------------------------------------------------------------------------------------------------------------------------- -- -- -- Interrupt is a generated once every 55 clock cycles to provide a 1us reference. -- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3. -- Timer: process(clk55MHz) begin if clk55MHz'event and clk55MHz='1' then if timer_count=54 then timer_count <= 0; timer_pulse <= '1'; else timer_count <= timer_count + 1; timer_pulse <= '0'; end if; if interrupt_ack = '1' then interrupt <= '0'; elsif timer_pulse = '1' then interrupt <= '1'; else interrupt <= interrupt; end if; end if; end process Timer; -- ---------------------------------------------------------------------------------------------------------------------------------- -- KCPSM3 input ports ---------------------------------------------------------------------------------------------------------------------------------- -- -- -- UART FIFO status signals to form a bus -- uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ; -- -- The inputs connect via a pipelined multiplexer -- input_ports: process(clk55MHz) begin if clk55MHz'event and clk55MHz='1' then case port_id(0) is -- read UART status at address 00 hex when '0' => in_port <= uart_status_port; -- read UART receive data at address 01 hex when '1' => in_port <= rx_data; -- Don't care used for all other addresses to ensure minimum logic implementation when others => in_port <= "XXXXXXXX"; end case; -- Form read strobe for UART receiver FIFO buffer. -- The fact that the read strobe will occur after the actual data is read by -- the KCPSM3 is acceptable because it is really means 'I have read you'! read_from_uart <= read_strobe and port_id(0); end if; end process input_ports; -- ---------------------------------------------------------------------------------------------------------------------------------- -- KCPSM3 output ports ---------------------------------------------------------------------------------------------------------------------------------- -- -- adding the output registers to the clock processor output_ports: process(clk55MHz) begin if clk55MHz'event and clk55MHz='1' then if write_strobe='1' then -- Alarm register at address 00 hex with data bit0 providing control if port_id(0)='0' then alarm <= out_port(0); end if; end if; end if; end process output_ports; -- -- write to UART transmitter FIFO buffer at address 01 hex. -- This is a combinatorial decode because the FIFO is the 'port register'. -- write_to_uart <= write_strobe and port_id(0); -- ---------------------------------------------------------------------------------------------------------------------------------- -- UART ---------------------------------------------------------------------------------------------------------------------------------- -- -- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros. -- Each contains an embedded 16-byte FIFO buffer. -- transmit: uart_tx port map ( data_in => out_port, write_buffer => write_to_uart, reset_buffer => '0', en_16_x_baud => en_16_x_baud, serial_out => tx, buffer_full => tx_full, buffer_half_full => tx_half_full, clk => clk55MHz ); receive: uart_rx port map ( serial_in => rx, data_out => rx_data, read_buffer => read_from_uart, reset_buffer => '0', en_16_x_baud => en_16_x_baud, buffer_data_present => rx_data_present, buffer_full => rx_full, buffer_half_full => rx_half_full, clk => clk55MHz ); -- -- Set baud rate to 38400 for the UART communications -- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 90 cycles at 55MHz -- -- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust -- the range of integers in the signal declaration for baud_count. -- Clock55MHz: ClockGen PORT MAP( CLKIN_IN => clk, RST_IN => rst, CLKFX_OUT => clk55MHz, CLKIN_IBUFG_OUT => open, CLK0_OUT => open, LOCKED_OUT => LED1 ); baud_timer: process(clk55MHz) begin if clk55MHz'event and clk55MHz='1' then if baud_count=89 then baud_count <= 0; en_16_x_baud <= '1'; else baud_count <= baud_count + 1; en_16_x_baud <= '0'; end if; end if; end process baud_timer; ---------------------------------------------------------------------------------------------------------------------------------- end Behavioral; ------------------------------------------------------------------------------------------------------------------------------------ -- -- END OF FILE uart_clock.vhd -- ------------------------------------------------------------------------------------------------------------------------------------