Release 7.1.01i - xst H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s --> Reading design: uart_clock.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "uart_clock.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "uart_clock" Output Format : NGC Target Device : xc3s200-4-ft256 ---- Source Options Top Module Name : uart_clock Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : uart_clock.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes enable_auto_floorplanning : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work. Architecture low_level_definition of Entity kcuart_rx is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work. Architecture low_level_definition of Entity bbfifo_16x8 is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work. Architecture low_level_definition of Entity kcuart_tx is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work. Architecture low_level_definition of Entity kcpsm3 is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work. Architecture low_level_definition of Entity uclock is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work. Architecture macro_level_definition of Entity uart_tx is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work. Architecture macro_level_definition of Entity uart_rx is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work. Architecture behavioral of Entity clockgen is up to date. Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 267: Mux is complete : default of case is discarded WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 357: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'ClockGen'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 357: Unconnected output port 'CLK0_OUT' of component 'ClockGen'. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 1" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0080" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = EAAA" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 04" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 7400" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 5A3C" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 2F" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 1000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 5400" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = D" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 41FC" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0001" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0001" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 3F" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6996" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6996" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = F3FF" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = F3" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = C" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 3" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0145" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0400" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000000000000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FFE2" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6E8A" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 1F" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6C" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 2" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 96" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0002" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = FE" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0010" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 4000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0100" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 00000000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6555" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = A999" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = A999" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = A999" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = A999" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT_00 = 0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance in unit . Set user-defined property "INIT_01 = 40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance in unit . Set user-defined property "INIT_02 = 5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance in unit . Set user-defined property "INIT_03 = 541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance in unit . Set user-defined property "INIT_04 = 5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance in unit . Set user-defined property "INIT_05 = 401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance in unit . Set user-defined property "INIT_06 = 1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance in unit . Set user-defined property "INIT_07 = 009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance in unit . Set user-defined property "INIT_08 = 000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance in unit . Set user-defined property "INIT_09 = 50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance in unit . Set user-defined property "INIT_0A = 013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance in unit . Set user-defined property "INIT_0B = 4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance in unit . Set user-defined property "INIT_0C = 810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance in unit . Set user-defined property "INIT_0D = 400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance in unit . Set user-defined property "INIT_0E = 0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance in unit . Set user-defined property "INIT_0F = 009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance in unit . Set user-defined property "INIT_10 = 009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance in unit . Set user-defined property "INIT_11 = 009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance in unit . Set user-defined property "INIT_12 = 0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance in unit . Set user-defined property "INIT_13 = 0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance in unit . Set user-defined property "INIT_14 = 009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance in unit . Set user-defined property "INIT_15 = A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance in unit . Set user-defined property "INIT_16 = F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance in unit . Set user-defined property "INIT_17 = 81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance in unit . Set user-defined property "INIT_18 = EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance in unit . Set user-defined property "INIT_19 = 82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance in unit . Set user-defined property "INIT_1A = E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance in unit . Set user-defined property "INIT_1B = 010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance in unit . Set user-defined property "INIT_1C = 5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance in unit . Set user-defined property "INIT_1D = 6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance in unit . Set user-defined property "INIT_1E = 1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance in unit . Set user-defined property "INIT_1F = 000000000000000000000000A0009200B80001E8701081010206920002060206" for instance in unit . Set user-defined property "INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INIT_3F = 43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INITP_00 = D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance in unit . Set user-defined property "INITP_01 = CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance in unit . Set user-defined property "INITP_02 = 4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance in unit . Set user-defined property "INITP_03 = 0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance in unit . Set user-defined property "INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance in unit . Set user-defined property "INITP_07 = F500000000000000000000000000000000000000000000000000000000000000" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4FF" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4FF" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4FF" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = E4FF" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 10" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0190" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 1540" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 94" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0180" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6606" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6606" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6606" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 6606" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0001" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = BFA0" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 257: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = C4" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 163: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 192: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 215: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 236: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0040" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 254: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 54" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 284: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 0000" for instance in unit . WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 331: Possible simulation mismatch on property of instance set by attribute. Set user-defined property "INIT = 8" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 98: Generating a Black Box for component . WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 102: Generating a Black Box for component . WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 106: Generating a Black Box for component . WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK90' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK180' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK270' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKDV' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X180' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKFX180' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'STATUS' of component 'DCM'. WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'PSDONE' of component 'DCM'. WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd". WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal > is assigned but never used. Found 1-bit register for signal . Found 7-bit up counter for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 6-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 13 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 2 6-bit up counter : 1 7-bit up counter : 1 # Registers : 6 1-bit register : 5 8-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block uart_clock, actual ratio is 8. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : uart_clock.ngr Top Level Output File Name : uart_clock Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 6 Macro Statistics : # Registers : 8 # 1-bit register : 5 # 6-bit register : 2 # 8-bit register : 1 # Adders/Subtractors : 2 # 6-bit adder : 2 Cell Usage : # BELS : 314 # GND : 1 # INV : 6 # LUT1 : 15 # LUT2 : 11 # LUT2_D : 1 # LUT2_L : 4 # LUT3 : 76 # LUT3_L : 5 # LUT4 : 61 # MULT_AND : 3 # MUXCY : 59 # MUXF5 : 11 # MUXF6 : 1 # VCC : 1 # XORCY : 59 # FlipFlops/Latches : 146 # FD : 37 # FDE : 29 # FDR : 47 # FDRE : 20 # FDRS : 1 # FDRSE : 10 # FDS : 2 # RAMS : 27 # RAM16X1D : 8 # RAM32X1S : 10 # RAM64X1S : 8 # RAMB16_S18 : 1 # Shifters : 36 # SRL16E : 36 # Clock Buffers : 2 # BUFG : 2 # IO Buffers : 6 # IBUF : 2 # IBUFG : 1 # OBUF : 3 # DCMs : 1 # DCM : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 198 out of 1920 10% Number of Slice Flip Flops: 146 out of 3840 3% Number of 4 input LUTs: 269 out of 3840 7% Number of bonded IOBs: 6 out of 173 3% Number of BRAMs: 1 out of 12 8% Number of GCLKs: 2 out of 8 25% Number of DCM_ADVs: 1 out of 4 25% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+--------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+--------------------------+-------+ clk | Clock55MHz/DCM_INST:CLKFX| 208 | -----------------------------------+--------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 10.263ns (Maximum Frequency: 97.439MHz) Minimum input arrival time before clock: 1.825ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 10.263ns (frequency: 97.439MHz) Total number of paths / destination ports: 1916 / 538 ------------------------------------------------------------------------- Delay: 9.330ns (Levels of Logic = 7) Source: processor/register_bit00 (RAM) Destination: transmit/buf/register_bit3 (FF) Source Clock: clk rising 1.1X Destination Clock: clk rising 1.1X Data Path: processor/register_bit00 to transmit/buf/register_bit3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAM16X1D:WCLK->DPO 1 1.784 0.869 processor/register_bit00 (processor/sy<0>) LUT3:I2->O 77 0.551 2.306 processor/operand_select_mux0 (port_id<0>) LUT2_D:I1->LO 1 0.551 0.295 write_to_uart1 (N41) LUT3:I1->O 9 0.551 1.124 transmit/buf/valid_lut (transmit/buf/valid_write) MUXCY:CI->O 1 0.064 0.000 transmit/buf/count_muxcy0 (transmit/buf/count_carry<0>) MUXCY:CI->O 1 0.064 0.000 transmit/buf/count_muxcy1 (transmit/buf/count_carry<1>) MUXCY:CI->O 0 0.064 0.000 transmit/buf/count_muxcy2 (transmit/buf/count_carry<2>) XORCY:CI->O 1 0.904 0.000 transmit/buf/count_xor3 (transmit/buf/next_count<3>) FDRE:D 0.203 transmit/buf/register_bit3 ---------------------------------------- Total 9.330ns (4.736ns logic, 4.594ns route) (50.8% logic, 49.2% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Offset: 1.825ns (Levels of Logic = 1) Source: rx (PAD) Destination: receive/kcuart/sync_reg (FF) Destination Clock: clk rising 1.1X Data Path: rx to receive/kcuart/sync_reg Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.821 0.801 rx_IBUF (rx_IBUF) FD:D 0.203 receive/kcuart/sync_reg ---------------------------------------- Total 1.825ns (1.024ns logic, 0.801ns route) (56.1% logic, 43.9% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 2 / 2 ------------------------------------------------------------------------- Offset: 7.165ns (Levels of Logic = 1) Source: transmit/kcuart/pipeline_serial (FF) Destination: tx (PAD) Source Clock: clk rising 1.1X Data Path: transmit/kcuart/pipeline_serial to tx Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRS:C->Q 1 0.720 0.801 transmit/kcuart/pipeline_serial (tx_OBUF) OBUF:I->O 5.644 tx_OBUF (tx) ---------------------------------------- Total 7.165ns (6.364ns logic, 0.801ns route) (88.8% logic, 11.2% route) ========================================================================= CPU : 22.10 / 22.41 s | Elapsed : 22.00 / 22.00 s --> Total memory usage is 114044 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 276 ( 0 filtered) Number of infos : 1 ( 0 filtered)