vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd"
vhdl work "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd"
vhdl work "ClockGen.vhd"
vhdl work "uart_clock.vhd"