Release 7.1.01i par H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

XSJJEFFW1-XP::  Thu Apr 14 14:51:27 2005

par -w -intstyle ise -ol std -t 1 uart_clock_map.ncd uart_clock.ncd
uart_clock.pcf 


Constraints file: uart_clock.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.36 2005-02-23".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs             6 out of 173     3%
      Number of LOCed IOBs             6 out of 6     100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  155 out of 1920    8%
      Number of SLICEMs               54 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989d8e) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
..............
Phase 4.8 (Checksum:9acaa3) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Writing design to file uart_clock.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 1445 unrouted;       REAL time: 1 secs 

Phase 2: 1220 unrouted;       REAL time: 2 secs 

Phase 3: 303 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|            clk55MHz |      BUFGMUX1| No   |  129 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file uart_clock.ncd



PAR done!