Release 7.1.01i Map H.39 Xilinx Mapping Report File for Design 'uart_clock' Design Information ------------------ Command Line : C:/Xilinx/ISE71/bin/nt/map.exe -ise c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo ck\PicoBlaze_Clock.ise -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -o uart_clock_map.ncd uart_clock.ngd uart_clock.pcf Target Device : xc3s200 Target Package : ft256 Target Speed : -4 Mapper Version : spartan3 -- $Revision: 1.26.6.4 $ Mapped Date : Thu Apr 14 14:51:23 2005 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 143 out of 3,840 3% Number of 4 input LUTs: 159 out of 3,840 4% Logic Distribution: Number of occupied Slices: 155 out of 1,920 8% Number of Slices containing only related logic: 155 out of 155 100% Number of Slices containing unrelated logic: 0 out of 155 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 276 out of 3,840 7% Number used as logic: 159 Number used as a route-thru: 13 Number used for Dual Port RAMs: 16 (Two LUTs used per Dual Port RAM) Number used for 32x1 RAMs: 52 (Two LUTs used per 32x1 RAM) Number used as Shift registers: 36 Number of bonded IOBs: 6 out of 173 3% IOB Flip Flops: 3 Number of Block RAMs: 1 out of 12 8% Number of GCLKs: 2 out of 8 25% Number of DCMs: 1 out of 4 25% Total equivalent gate count for design: 85,146 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 106 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Additional Device Resource Counts Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "Clock55MHz/CLK0_BUFG_INST" (output signal=Clock55MHz/CLK0_OUT), BUFG symbol "Clock55MHz/CLKFX_BUFG_INST" (output signal=clk55MHz) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp Clock55MHz/DCM_INST/Clock55MHz/DCM_INST, consult the device Interactive Data Sheet. Section 4 - Removed Logic Summary --------------------------------- 4 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK LUT1 N1_rt LUT1 N1_rt1 GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | LED1 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | alarm | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | clk | IOB | INPUT | LVCMOS25 | | | | | | | rst | IOB | INPUT | LVCMOS25 | | | | | | | rx | IOB | INPUT | LVCMOS25 | | | INFF1 | | | | tx | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design. Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details -------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Additional Device Resource Counts ---------------------------------------------- Number of JTAG Gates for IOBs = 6 Number of Equivalent Gates for Design = 85,146 Number of RPM Macros = 0 Number of Hard Macros = 0 DCIRESETs = 0 CAPTUREs = 0 BSCANs = 0 STARTUPs = 0 DCMs = 1 GCLKs = 2 ICAPs = 0 18X18 Multipliers = 0 Block RAMs = 1 Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 75 IOB Dual-Rate Flops not driven by LUTs = 0 IOB Dual-Rate Flops = 0 IOB Slave Pads = 0 IOB Master Pads = 0 IOB Latches not driven by LUTs = 0 IOB Latches = 0 IOB Flip Flops not driven by LUTs = 2 IOB Flip Flops = 3 Unbonded IOBs = 0 Bonded IOBs = 6 XORs = 59 CARRY_INITs = 37 CARRY_SKIPs = 0 CARRY_MUXes = 59 Shift Registers = 36 Static Shift Registers = 20 Dynamic Shift Registers = 16 16x1 ROMs = 0 16x1 RAMs = 0 32x1 RAMs = 26 Dual Port RAMs = 8 MUXFs = 46 MULT_ANDs = 3 4 input LUTs used as Route-Thrus = 13 4 input LUTs = 159 Slice Latches not driven by LUTs = 0 Slice Latches = 0 Slice Flip Flops not driven by LUTs = 73 Slice Flip Flops = 143 SliceMs = 54 SliceLs = 101 Slices = 155 F6 Muxes = 1 F5 Muxes = 11 F8 Muxes = 0 F7 Muxes = 0 Number of LUT signals with 4 loads = 1 Number of LUT signals with 3 loads = 0 Number of LUT signals with 2 loads = 49 Number of LUT signals with 1 load = 90 NGM Average fanout of LUT = 2.28 NGM Maximum fanout of LUT = 21 NGM Average fanin for LUT = 3.2390 Number of LUT symbols = 159