Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.00 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.00 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: embedded_kcpsm3.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "embedded_kcpsm3.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "embedded_kcpsm3"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : embedded_kcpsm3
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : embedded_kcpsm3.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Entity <kcpsm3> compiled.
Entity <kcpsm3> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd" in Library work.
Entity <embedded_kcpsm3> compiled.
Entity <embedded_kcpsm3> (Architecture <connectivity>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <embedded_kcpsm3> (Architecture <connectivity>).
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd" line 94: Generating a Black Box for component <prog_rom>.
Entity <embedded_kcpsm3> analyzed. Unit <embedded_kcpsm3> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <embedded_kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd".
Unit <embedded_kcpsm3> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <embedded_kcpsm3> ...

Optimizing unit <kcpsm3> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block embedded_kcpsm3, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : embedded_kcpsm3.ngr
Top Level Output File Name         : embedded_kcpsm3
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 30

Cell Usage :
# BELS                             : 202
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 4
#      LUT2                        : 5
#      LUT3                        : 69
#      LUT4                        : 33
#      MUXCY                       : 39
#      MUXF5                       : 9
#      VCC                         : 1
#      XORCY                       : 37
# FlipFlops/Latches                : 76
#      FD                          : 24
#      FDE                         : 2
#      FDR                         : 30
#      FDRE                        : 8
#      FDRSE                       : 10
#      FDS                         : 2
# RAMS                             : 26
#      RAM16X1D                    : 8
#      RAM32X1S                    : 10
#      RAM64X1S                    : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 29
#      IBUF                        : 10
#      OBUF                        : 19
# Others                           : 1
#      prog_rom                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     132  out of   1920     6%  
 Number of Slice Flip Flops:            76  out of   3840     1%  
 Number of 4 input LUTs:               171  out of   3840     4%  
 Number of bonded IOBs:                 30  out of    173    17%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 102   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.303ns (Maximum Frequency: 120.438MHz)
   Minimum input arrival time before clock: 8.287ns
   Maximum output required time after clock: 10.902ns
   Maximum combinational path delay: 10.803ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.303ns (frequency: 120.438MHz)
  Total number of paths / destination ports: 1096 / 275
-------------------------------------------------------------------------
Delay:               8.303ns (Levels of Logic = 13)
  Source:            processor/carry_flag_flop (FF)
  Destination:       processor/register_bit9 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: processor/carry_flag_flop to processor/register_bit9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   0.720   1.256  processor/carry_flag_flop (processor/carry_flag)
     LUT4:I0->O            2   0.551   1.072  processor/condition_met_lut (processor/condition_met)
     LUT3:I1->O           11   0.551   1.483  processor/normal_count_lut (processor/normal_count)
     LUT3:I0->O            1   0.551   0.000  processor/value_select_mux0 (processor/pc_value<0>)
     MUXCY:S->O            1   0.500   0.000  processor/pc_value_muxcy0 (processor/pc_value_carry<0>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy1 (processor/pc_value_carry<1>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy2 (processor/pc_value_carry<2>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy3 (processor/pc_value_carry<3>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy4 (processor/pc_value_carry<4>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy5 (processor/pc_value_carry<5>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy6 (processor/pc_value_carry<6>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy7 (processor/pc_value_carry<7>)
     MUXCY:CI->O           0   0.064   0.000  processor/pc_value_muxcy8 (processor/pc_value_carry<8>)
     XORCY:CI->O           1   0.904   0.000  processor/pc_value_xor9 (processor/inc_pc_value<9>)
     FDRSE:D                   0.203          processor/register_bit9
    ----------------------------------------
    Total                      8.303ns (4.492ns logic, 3.811ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 2722 / 223
-------------------------------------------------------------------------
Offset:              8.287ns (Levels of Logic = 13)
  Source:            program:instruction<14> (PAD)
  Destination:       processor/register_bit9 (FF)
  Destination Clock: clk rising

  Data Path: program:instruction<14> to processor/register_bit9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    prog_rom:instruction<14>   27   0.000   2.163  program (instruction<14>)
     LUT4:I0->O            1   0.551   0.869  processor/move_group_lut (processor/move_group)
     LUT3:I2->O           11   0.551   1.483  processor/normal_count_lut (processor/normal_count)
     LUT3:I0->O            1   0.551   0.000  processor/value_select_mux0 (processor/pc_value<0>)
     MUXCY:S->O            1   0.500   0.000  processor/pc_value_muxcy0 (processor/pc_value_carry<0>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy1 (processor/pc_value_carry<1>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy2 (processor/pc_value_carry<2>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy3 (processor/pc_value_carry<3>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy4 (processor/pc_value_carry<4>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy5 (processor/pc_value_carry<5>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy6 (processor/pc_value_carry<6>)
     MUXCY:CI->O           1   0.064   0.000  processor/pc_value_muxcy7 (processor/pc_value_carry<7>)
     MUXCY:CI->O           0   0.064   0.000  processor/pc_value_muxcy8 (processor/pc_value_carry<8>)
     XORCY:CI->O           1   0.904   0.000  processor/pc_value_xor9 (processor/inc_pc_value<9>)
     FDRSE:D                   0.203          processor/register_bit9
    ----------------------------------------
    Total                      8.287ns (3.772ns logic, 4.515ns route)
                                       (45.5% logic, 54.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 29 / 29
-------------------------------------------------------------------------
Offset:              10.902ns (Levels of Logic = 2)
  Source:            processor/register_bit30 (RAM)
  Destination:       port_id<3> (PAD)
  Source Clock:      clk rising

  Data Path: processor/register_bit30 to port_id<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAM16X1D:WCLK->DPO    1   1.784   0.869  processor/register_bit30 (processor/sy<3>)
     LUT3:I2->O           67   0.551   2.054  processor/operand_select_mux3 (port_id_3_OBUF)
     OBUF:I->O                 5.644          port_id_3_OBUF (port_id<3>)
    ----------------------------------------
    Total                     10.902ns (7.979ns logic, 2.923ns route)
                                       (73.2% logic, 26.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 81 / 17
-------------------------------------------------------------------------
Delay:               10.803ns (Levels of Logic = 3)
  Source:            program:instruction<4> (PAD)
  Destination:       port_id<3> (PAD)

  Data Path: program:instruction<4> to port_id<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    prog_rom:instruction<4>   10   0.000   1.134  program (instruction<4>)
     RAM16X1D:DPRA0->DPO    1   0.551   0.869  processor/register_bit30 (processor/sy<3>)
     LUT3:I2->O           67   0.551   2.054  processor/operand_select_mux3 (port_id_3_OBUF)
     OBUF:I->O                 5.644          port_id_3_OBUF (port_id<3>)
    ----------------------------------------
    Total                     10.803ns (6.746ns logic, 4.057ns route)
                                       (62.4% logic, 37.6% route)

=========================================================================
CPU : 13.65 / 14.80 s | Elapsed : 14.00 / 14.00 s
 
--> 

Total memory usage is 110972 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  136 (   0 filtered)
Number of infos    :    0 (   0 filtered)