Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Entity <kcpsm3> compiled.
Entity <kcpsm3> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd" in Library work.
Entity <embedded_kcpsm3> compiled.
Entity <embedded_kcpsm3> (Architecture <connectivity>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <embedded_kcpsm3> (Architecture <connectivity>).
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd" line 94: Generating a Black Box for component <prog_rom>.
Entity <embedded_kcpsm3> analyzed. Unit <embedded_kcpsm3> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <embedded_kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/embedded_kcpsm3.vhd".
Unit <embedded_kcpsm3> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <embedded_kcpsm3> ...

Optimizing unit <kcpsm3> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block embedded_kcpsm3, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     132  out of   1920     6%  
 Number of Slice Flip Flops:            76  out of   3840     1%  
 Number of 4 input LUTs:               171  out of   3840     4%  
 Number of bonded IOBs:                 30  out of    173    17%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 102   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.303ns (Maximum Frequency: 120.438MHz)
   Minimum input arrival time before clock: 8.287ns
   Maximum output required time after clock: 10.902ns
   Maximum combinational path delay: 10.803ns

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Entity <kcuart_rx> compiled.
Entity <kcuart_rx> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Entity <bbfifo_16x8> compiled.
Entity <bbfifo_16x8> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Entity <kcuart_tx> compiled.
Entity <kcuart_tx> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Entity <uclock> compiled.
Entity <uclock> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Entity <uart_tx> compiled.
Entity <uart_tx> (Architecture <macro_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Entity <uart_rx> compiled.
Entity <uart_rx> (Architecture <macro_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/vhdl/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
Entity <uart_clock> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart_clock> (Architecture <Behavioral>).
INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/vhdl/PicoBlaze_Clock/uart_clock.vhd" line 241: Mux is complete : default of case is discarded
Entity <uart_clock> analyzed. Unit <uart_clock> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.

Analyzing Entity <uclock> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_08> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_09> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_10> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_11> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_12> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_13> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_14> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_15> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_16> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_17> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_18> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_19> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_20> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_21> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_22> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_23> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_24> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_25> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_26> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_27> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_28> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_29> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_30> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_31> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_32> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_33> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_34> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_35> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_36> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_37> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_38> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_39> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3F> of instance <ram_1024_x_18> set by attribute.
    Set user-defined property "INIT_00 =  0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_01 =  40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_02 =  5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_03 =  541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_04 =  5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_05 =  401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_06 =  1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_07 =  009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_08 =  000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_09 =  50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0A =  013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0B =  4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0C =  810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0D =  400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0E =  0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0F =  009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_10 =  009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_11 =  009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_12 =  0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_13 =  0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_14 =  009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_15 =  A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_16 =  F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_17 =  81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_18 =  EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_19 =  82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1A =  E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1B =  010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1C =  5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1D =  6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1E =  1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1F =  000000000000000000000000A0009200B80001E8701081010206920002060206" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3F =  43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_00 =  D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_01 =  CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_02 =  4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_03 =  0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_07 =  F500000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
Entity <uclock> analyzed. Unit <uclock> generated.

Analyzing Entity <uart_tx> (Architecture <macro_level_definition>).
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing Entity <kcuart_tx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property <INIT> of instance <mux1_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property <INIT> of instance <mux2_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property <INIT> of instance <mux3_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <mux4_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut0> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut1> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut2> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property <INIT> of instance <ready_lut> set by attribute.
    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property <INIT> of instance <start_lut> set by attribute.
    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property <INIT> of instance <run_lut> set by attribute.
    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property <INIT> of instance <hot_state_lut> set by attribute.
    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property <INIT> of instance <delay14_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property <INIT> of instance <stop_lut> set by attribute.
    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property <INIT> of instance <complete_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.

Analyzing Entity <bbfifo_16x8> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl4> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl5> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl6> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl7> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property <INIT> of instance <full_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simulation mismatch on property <INIT> of instance <dp_lut> set by attribute.
    Set user-defined property "INIT =  BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 257: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  C4" for instance <valid_lut> in unit <bbfifo_16x8>.
Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.

Analyzing Entity <uart_rx> (Architecture <macro_level_definition>).
Entity <uart_rx> analyzed. Unit <uart_rx> generated.

Analyzing Entity <kcuart_rx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl0> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <delay15_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 192: Possible simulation mismatch on property <INIT> of instance <start_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <start_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <edge_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <edge_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 236: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  0040" for instance <valid_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 254: Possible simulation mismatch on property <INIT> of instance <purge_lut> set by attribute.
    Set user-defined property "INIT =  54" for instance <purge_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 284: Possible simulation mismatch on property <INIT> of instance <delay15_srl00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl00> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl8> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl8> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 331: Possible simulation mismatch on property <INIT> of instance <strobe_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <strobe_lut> in unit <kcuart_rx>.
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcuart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd".
Unit <kcuart_rx> synthesized.


Synthesizing Unit <bbfifo_16x8>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd".
Unit <bbfifo_16x8> synthesized.


Synthesizing Unit <kcuart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd".
Unit <kcuart_tx> synthesized.


Synthesizing Unit <uart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd".
Unit <uart_rx> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd".
Unit <uart_tx> synthesized.


Synthesizing Unit <uclock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD".
Unit <uclock> synthesized.


Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <uart_clock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/vhdl/PicoBlaze_Clock/uart_clock.vhd".
WARNING:Xst:646 - Signal <port_id<7:1>> is assigned but never used.
    Found 1-bit register for signal <alarm>.
    Found 7-bit up counter for signal <baud_count>.
    Found 1-bit register for signal <en_16_x_baud>.
    Found 8-bit register for signal <in_port>.
    Found 1-bit register for signal <interrupt>.
    Found 1-bit register for signal <read_from_uart>.
    Found 6-bit up counter for signal <timer_count>.
    Found 1-bit register for signal <timer_pulse>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <uart_clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 6-bit up counter                  : 1
 7-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 5
 8-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uart_clock> ...

Optimizing unit <kcuart_rx> ...

Optimizing unit <bbfifo_16x8> ...

Optimizing unit <kcpsm3> ...

Optimizing unit <kcuart_tx> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart_clock, actual ratio is 8.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     196  out of   1920    10%  
 Number of Slice Flip Flops:           146  out of   3840     3%  
 Number of 4 input LUTs:               269  out of   3840     7%  
 Number of bonded IOBs:                  4  out of    173     2%  
 Number of BRAMs:                        1  out of     12     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 208   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.330ns (Maximum Frequency: 107.183MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo
ck/_ngo -nt timestamp -i -p xc3s200-ft256-4 uart_clock.ngc uart_clock.ngd 

Reading NGO file
'C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/vhdl/PicoBlaze_Cl
ock/uart_clock.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart_clock.ngd" ...

Writing NGDBUILD log file "uart_clock.bld"...

NGDBUILD done.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         143 out of   3,840    3%
  Number of 4 input LUTs:             159 out of   3,840    4%
Logic Distribution:
  Number of occupied Slices:                          156 out of   1,920    8%
    Number of Slices containing only related logic:     156 out of     156  100%
    Number of Slices containing unrelated logic:          0 out of     156    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            276 out of   3,840    7%
  Number used as logic:                159
  Number used as a route-thru:          13
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            52
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:       36
  Number of bonded IOBs:                4 out of     173    2%
    IOB Flip Flops:                     3
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  78,143
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  106 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "uart_clock_map.mrp" for details.




Started process "Place & Route".




Constraints file: uart_clock.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.36 2005-02-23".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             4 out of 173     2%
      Number of LOCed IOBs             0 out of 4       0%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  156 out of 1920    8%
      Number of SLICEMs               54 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989cdf) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
..................................................
Phase 6.8 (Checksum:9bbadf) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file uart_clock.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 1435 unrouted;       REAL time: 3 secs 

Phase 2: 1213 unrouted;       REAL time: 3 secs 

Phase 3: 363 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 


Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX6| No   |  128 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file uart_clock.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Thu Apr 14 13:25:04 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo
ck/_ngo -nt timestamp -uc uart_clock.ucf -p xc3s200-ft256-4 uart_clock.ngc
uart_clock.ngd 

Reading NGO file
'C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/uart_clock.ngc' ...

Applying constraints in "uart_clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart_clock.ngd" ...

Writing NGDBUILD log file "uart_clock.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         143 out of   3,840    3%
  Number of 4 input LUTs:             159 out of   3,840    4%
Logic Distribution:
  Number of occupied Slices:                          156 out of   1,920    8%
    Number of Slices containing only related logic:     156 out of     156  100%
    Number of Slices containing unrelated logic:          0 out of     156    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            276 out of   3,840    7%
  Number used as logic:                159
  Number used as a route-thru:          13
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            52
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:       36
  Number of bonded IOBs:                4 out of     173    2%
    IOB Flip Flops:                     3
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  78,143
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  106 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "uart_clock_map.mrp" for details.




Started process "Place & Route".




Constraints file: uart_clock.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.36 2005-02-23".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             4 out of 173     2%
      Number of LOCed IOBs             4 out of 4     100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  156 out of 1920    8%
      Number of SLICEMs               54 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989cdf) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
................
Phase 4.8 (Checksum:9a94f7) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Writing design to file uart_clock.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 1435 unrouted;       REAL time: 1 secs 

Phase 2: 1213 unrouted;       REAL time: 1 secs 

Phase 3: 300 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |  128 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file uart_clock.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Thu Apr 14 13:40:15 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo
ck/_ngo -nt timestamp -uc uart_clock.ucf -p xc3s200-ft256-4 uart_clock.ngc
uart_clock.ngd 

Reading NGO file
'C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/uart_clock.ngc' ...

Applying constraints in "uart_clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart_clock.ngd" ...

Writing NGDBUILD log file "uart_clock.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         143 out of   3,840    3%
  Number of 4 input LUTs:             159 out of   3,840    4%
Logic Distribution:
  Number of occupied Slices:                          156 out of   1,920    8%
    Number of Slices containing only related logic:     156 out of     156  100%
    Number of Slices containing unrelated logic:          0 out of     156    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            276 out of   3,840    7%
  Number used as logic:                159
  Number used as a route-thru:          13
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            52
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:       36
  Number of bonded IOBs:                4 out of     173    2%
    IOB Flip Flops:                     3
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  78,143
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  106 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "uart_clock_map.mrp" for details.




Started process "Place & Route".




Constraints file: uart_clock.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.36 2005-02-23".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             4 out of 173     2%
      Number of LOCed IOBs             4 out of 4     100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  156 out of 1920    8%
      Number of SLICEMs               54 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989cdf) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
..............
Phase 4.8 (Checksum:9a9083) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Writing design to file uart_clock.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 1435 unrouted;       REAL time: 1 secs 

Phase 2: 1213 unrouted;       REAL time: 1 secs 

Phase 3: 323 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 1 secs 


Total REAL time to Router completion: 1 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |  128 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file uart_clock.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Thu Apr 14 13:48:09 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo
ck/_ngo -nt timestamp -uc uart_clock.ucf -p xc3s200-ft256-4 uart_clock.ngc
uart_clock.ngd 

Reading NGO file
'C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/uart_clock.ngc' ...

Applying constraints in "uart_clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart_clock.ngd" ...

Writing NGDBUILD log file "uart_clock.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         143 out of   3,840    3%
  Number of 4 input LUTs:             159 out of   3,840    4%
Logic Distribution:
  Number of occupied Slices:                          156 out of   1,920    8%
    Number of Slices containing only related logic:     156 out of     156  100%
    Number of Slices containing unrelated logic:          0 out of     156    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            276 out of   3,840    7%
  Number used as logic:                159
  Number used as a route-thru:          13
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            52
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:       36
  Number of bonded IOBs:                4 out of     173    2%
    IOB Flip Flops:                     3
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  78,143
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  106 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "uart_clock_map.mrp" for details.




Started process "Place & Route".




Constraints file: uart_clock.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.36 2005-02-23".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             4 out of 173     2%
      Number of LOCed IOBs             4 out of 4     100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  156 out of 1920    8%
      Number of SLICEMs               54 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989cdf) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
................
Phase 4.8 (Checksum:9a94f7) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Writing design to file uart_clock.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 1435 unrouted;       REAL time: 1 secs 

Phase 2: 1213 unrouted;       REAL time: 1 secs 

Phase 3: 300 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 1 secs 


Total REAL time to Router completion: 1 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |  128 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file uart_clock.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx/ISE71.
   "uart_clock" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Thu Apr 14 13:49:31 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2vhdl: Completed successfully




Started process "View HDL Instantiation Template".

Compiling vhdl file
"C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/ClockGen.vhd" in Library work.
Entity <ClockGen> compiled.
Entity <ClockGen> (Architecture <BEHAVIORAL>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2vhdl: Completed successfully




Started process "View HDL Instantiation Template".

Compiling vhdl file
"C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/ClockGen.vhd" in Library work.
Entity <ClockGen> compiled.
Entity <ClockGen> (Architecture <BEHAVIORAL>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Entity <ClockGen> compiled.
Entity <ClockGen> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
ERROR:HDLParsers:164 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" Line 367. parse error, unexpected COMMA
--> 

Total memory usage is 87180 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Architecture behavioral of Entity clockgen is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
ERROR:HDLParsers:3312 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" Line 370. Undefined symbol 'LED1'.
ERROR:HDLParsers:1209 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" Line 370. LED1: Undefined symbol (last report in this block)
--> 

Total memory usage is 87180 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Architecture behavioral of Entity clockgen is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
Entity <uart_clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart_clock> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 262: Mux is complete : default of case is discarded
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'ClockGen'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLK0_OUT' of component 'ClockGen'.
Entity <uart_clock> analyzed. Unit <uart_clock> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.

Analyzing Entity <uclock> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_08> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_09> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_10> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_11> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_12> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_13> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_14> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_15> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_16> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_17> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_18> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_19> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_20> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_21> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_22> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_23> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_24> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_25> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_26> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_27> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_28> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_29> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_30> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_31> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_32> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_33> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_34> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_35> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_36> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_37> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_38> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_39> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3F> of instance <ram_1024_x_18> set by attribute.
    Set user-defined property "INIT_00 =  0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_01 =  40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_02 =  5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_03 =  541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_04 =  5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_05 =  401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_06 =  1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_07 =  009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_08 =  000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_09 =  50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0A =  013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0B =  4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0C =  810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0D =  400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0E =  0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0F =  009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_10 =  009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_11 =  009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_12 =  0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_13 =  0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_14 =  009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_15 =  A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_16 =  F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_17 =  81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_18 =  EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_19 =  82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1A =  E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1B =  010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1C =  5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1D =  6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1E =  1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1F =  000000000000000000000000A0009200B80001E8701081010206920002060206" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3F =  43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_00 =  D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_01 =  CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_02 =  4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_03 =  0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_07 =  F500000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
Entity <uclock> analyzed. Unit <uclock> generated.

Analyzing Entity <uart_tx> (Architecture <macro_level_definition>).
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing Entity <kcuart_tx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property <INIT> of instance <mux1_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property <INIT> of instance <mux2_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property <INIT> of instance <mux3_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <mux4_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut0> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut1> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut2> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property <INIT> of instance <ready_lut> set by attribute.
    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property <INIT> of instance <start_lut> set by attribute.
    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property <INIT> of instance <run_lut> set by attribute.
    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property <INIT> of instance <hot_state_lut> set by attribute.
    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property <INIT> of instance <delay14_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property <INIT> of instance <stop_lut> set by attribute.
    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property <INIT> of instance <complete_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.

Analyzing Entity <bbfifo_16x8> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl4> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl5> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl6> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl7> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property <INIT> of instance <full_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simulation mismatch on property <INIT> of instance <dp_lut> set by attribute.
    Set user-defined property "INIT =  BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 257: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  C4" for instance <valid_lut> in unit <bbfifo_16x8>.
Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.

Analyzing Entity <uart_rx> (Architecture <macro_level_definition>).
Entity <uart_rx> analyzed. Unit <uart_rx> generated.

Analyzing Entity <kcuart_rx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl0> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <delay15_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 192: Possible simulation mismatch on property <INIT> of instance <start_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <start_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <edge_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <edge_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 236: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  0040" for instance <valid_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 254: Possible simulation mismatch on property <INIT> of instance <purge_lut> set by attribute.
    Set user-defined property "INIT =  54" for instance <purge_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 284: Possible simulation mismatch on property <INIT> of instance <delay15_srl00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl00> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl8> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl8> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 331: Possible simulation mismatch on property <INIT> of instance <strobe_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <strobe_lut> in unit <kcuart_rx>.
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.

Analyzing Entity <ClockGen> (Architecture <behavioral>).
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 98: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 102: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 106: Generating a Black Box for component <BUFG>.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK90' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK270' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKDV' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKFX180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'STATUS' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'PSDONE' of component 'DCM'.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Generating a Black Box for component <DCM>.
Entity <ClockGen> analyzed. Unit <ClockGen> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcuart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd".
Unit <kcuart_rx> synthesized.


Synthesizing Unit <bbfifo_16x8>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd".
Unit <bbfifo_16x8> synthesized.


Synthesizing Unit <kcuart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd".
Unit <kcuart_tx> synthesized.


Synthesizing Unit <ClockGen>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd".
Unit <ClockGen> synthesized.


Synthesizing Unit <uart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd".
Unit <uart_rx> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd".
Unit <uart_tx> synthesized.


Synthesizing Unit <uclock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD".
Unit <uclock> synthesized.


Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <uart_clock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd".
WARNING:Xst:646 - Signal <port_id<7:1>> is assigned but never used.
    Found 1-bit register for signal <alarm>.
    Found 7-bit up counter for signal <baud_count>.
    Found 1-bit register for signal <en_16_x_baud>.
    Found 8-bit register for signal <in_port>.
    Found 1-bit register for signal <interrupt>.
    Found 1-bit register for signal <read_from_uart>.
    Found 6-bit up counter for signal <timer_count>.
    Found 1-bit register for signal <timer_pulse>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <uart_clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 6-bit up counter                  : 1
 7-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 5
 8-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uart_clock> ...

Optimizing unit <kcuart_rx> ...

Optimizing unit <bbfifo_16x8> ...

Optimizing unit <kcpsm3> ...

Optimizing unit <kcuart_tx> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
ERROR:Xst:2035 - Port <clk> has illegal connection. Port is connected to input buffer and following ports:
   Port CLK of instance transmit/buf/data_srl1 in unit uart_clock with type SRL16E
CPU : 19.64 / 19.95 s | Elapsed : 19.00 / 20.00 s
 
--> 

Total memory usage is 114044 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  275 (   0 filtered)
Number of infos    :    1 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Architecture behavioral of Entity clockgen is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
Entity <uart_clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart_clock> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 267: Mux is complete : default of case is discarded
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'ClockGen'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLK0_OUT' of component 'ClockGen'.
Entity <uart_clock> analyzed. Unit <uart_clock> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.

Analyzing Entity <uclock> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_08> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_09> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_10> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_11> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_12> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_13> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_14> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_15> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_16> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_17> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_18> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_19> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_20> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_21> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_22> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_23> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_24> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_25> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_26> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_27> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_28> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_29> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_30> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_31> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_32> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_33> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_34> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_35> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_36> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_37> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_38> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_39> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3F> of instance <ram_1024_x_18> set by attribute.
    Set user-defined property "INIT_00 =  0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_01 =  40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_02 =  5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_03 =  541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_04 =  5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_05 =  401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_06 =  1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_07 =  009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_08 =  000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_09 =  50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0A =  013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0B =  4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0C =  810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0D =  400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0E =  0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0F =  009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_10 =  009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_11 =  009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_12 =  0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_13 =  0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_14 =  009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_15 =  A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_16 =  F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_17 =  81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_18 =  EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_19 =  82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1A =  E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1B =  010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1C =  5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1D =  6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1E =  1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1F =  000000000000000000000000A0009200B80001E8701081010206920002060206" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3F =  43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_00 =  D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_01 =  CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_02 =  4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_03 =  0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_07 =  F500000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
Entity <uclock> analyzed. Unit <uclock> generated.

Analyzing Entity <uart_tx> (Architecture <macro_level_definition>).
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing Entity <kcuart_tx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property <INIT> of instance <mux1_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property <INIT> of instance <mux2_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property <INIT> of instance <mux3_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <mux4_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut0> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut1> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut2> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property <INIT> of instance <ready_lut> set by attribute.
    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property <INIT> of instance <start_lut> set by attribute.
    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property <INIT> of instance <run_lut> set by attribute.
    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property <INIT> of instance <hot_state_lut> set by attribute.
    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property <INIT> of instance <delay14_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property <INIT> of instance <stop_lut> set by attribute.
    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property <INIT> of instance <complete_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.

Analyzing Entity <bbfifo_16x8> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl4> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl5> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl6> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl7> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property <INIT> of instance <full_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simulation mismatch on property <INIT> of instance <dp_lut> set by attribute.
    Set user-defined property "INIT =  BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 257: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  C4" for instance <valid_lut> in unit <bbfifo_16x8>.
Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.

Analyzing Entity <uart_rx> (Architecture <macro_level_definition>).
Entity <uart_rx> analyzed. Unit <uart_rx> generated.

Analyzing Entity <kcuart_rx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl0> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <delay15_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 192: Possible simulation mismatch on property <INIT> of instance <start_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <start_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <edge_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <edge_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 236: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  0040" for instance <valid_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 254: Possible simulation mismatch on property <INIT> of instance <purge_lut> set by attribute.
    Set user-defined property "INIT =  54" for instance <purge_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 284: Possible simulation mismatch on property <INIT> of instance <delay15_srl00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl00> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl8> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl8> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 331: Possible simulation mismatch on property <INIT> of instance <strobe_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <strobe_lut> in unit <kcuart_rx>.
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.

Analyzing Entity <ClockGen> (Architecture <behavioral>).
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 98: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 106: Generating a Black Box for component <BUFG>.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK90' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK270' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKDV' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKFX180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'STATUS' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'PSDONE' of component 'DCM'.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Generating a Black Box for component <DCM>.
Entity <ClockGen> analyzed. Unit <ClockGen> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcuart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd".
Unit <kcuart_rx> synthesized.


Synthesizing Unit <bbfifo_16x8>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd".
Unit <bbfifo_16x8> synthesized.


Synthesizing Unit <kcuart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd".
Unit <kcuart_tx> synthesized.


Synthesizing Unit <ClockGen>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd".
Unit <ClockGen> synthesized.


Synthesizing Unit <uart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd".
Unit <uart_rx> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd".
Unit <uart_tx> synthesized.


Synthesizing Unit <uclock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD".
Unit <uclock> synthesized.


Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <uart_clock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd".
WARNING:Xst:646 - Signal <port_id<7:1>> is assigned but never used.
    Found 1-bit register for signal <alarm>.
    Found 7-bit up counter for signal <baud_count>.
    Found 1-bit register for signal <en_16_x_baud>.
    Found 8-bit register for signal <in_port>.
    Found 1-bit register for signal <interrupt>.
    Found 1-bit register for signal <read_from_uart>.
    Found 6-bit up counter for signal <timer_count>.
    Found 1-bit register for signal <timer_pulse>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <uart_clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 6-bit up counter                  : 1
 7-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 5
 8-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uart_clock> ...

Optimizing unit <kcuart_rx> ...

Optimizing unit <bbfifo_16x8> ...

Optimizing unit <kcpsm3> ...

Optimizing unit <kcuart_tx> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
ERROR:Xst:2035 - Port <clk> has illegal connection. Port is connected to input buffer and following ports:
   Port CLK of instance transmit/buf/data_srl1 in unit uart_clock with type SRL16E
CPU : 19.32 / 19.69 s | Elapsed : 20.00 / 20.00 s
 
--> 

Total memory usage is 114044 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  274 (   0 filtered)
Number of infos    :    1 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Architecture behavioral of Entity clockgen is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
Entity <uart_clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart_clock> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 267: Mux is complete : default of case is discarded
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'ClockGen'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 364: Unconnected output port 'CLK0_OUT' of component 'ClockGen'.
Entity <uart_clock> analyzed. Unit <uart_clock> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.

Analyzing Entity <uclock> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_08> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_09> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_10> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_11> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_12> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_13> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_14> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_15> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_16> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_17> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_18> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_19> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_20> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_21> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_22> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_23> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_24> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_25> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_26> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_27> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_28> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_29> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_30> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_31> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_32> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_33> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_34> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_35> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_36> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_37> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_38> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_39> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3F> of instance <ram_1024_x_18> set by attribute.
    Set user-defined property "INIT_00 =  0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_01 =  40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_02 =  5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_03 =  541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_04 =  5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_05 =  401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_06 =  1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_07 =  009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_08 =  000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_09 =  50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0A =  013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0B =  4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0C =  810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0D =  400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0E =  0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0F =  009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_10 =  009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_11 =  009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_12 =  0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_13 =  0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_14 =  009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_15 =  A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_16 =  F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_17 =  81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_18 =  EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_19 =  82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1A =  E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1B =  010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1C =  5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1D =  6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1E =  1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1F =  000000000000000000000000A0009200B80001E8701081010206920002060206" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3F =  43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_00 =  D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_01 =  CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_02 =  4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_03 =  0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_07 =  F500000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
Entity <uclock> analyzed. Unit <uclock> generated.

Analyzing Entity <uart_tx> (Architecture <macro_level_definition>).
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing Entity <kcuart_tx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property <INIT> of instance <mux1_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property <INIT> of instance <mux2_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property <INIT> of instance <mux3_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <mux4_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut0> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut1> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut2> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property <INIT> of instance <ready_lut> set by attribute.
    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property <INIT> of instance <start_lut> set by attribute.
    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property <INIT> of instance <run_lut> set by attribute.
    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property <INIT> of instance <hot_state_lut> set by attribute.
    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property <INIT> of instance <delay14_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property <INIT> of instance <stop_lut> set by attribute.
    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property <INIT> of instance <complete_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.

Analyzing Entity <bbfifo_16x8> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl4> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl5> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl6> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl7> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property <INIT> of instance <full_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simulation mismatch on property <INIT> of instance <dp_lut> set by attribute.
    Set user-defined property "INIT =  BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 257: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  C4" for instance <valid_lut> in unit <bbfifo_16x8>.
Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.

Analyzing Entity <uart_rx> (Architecture <macro_level_definition>).
Entity <uart_rx> analyzed. Unit <uart_rx> generated.

Analyzing Entity <kcuart_rx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl0> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 141: Possible simulation mismatch on property <INIT> of instance <delay15_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <delay15_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 192: Possible simulation mismatch on property <INIT> of instance <start_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <start_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <edge_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <edge_srl> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 236: Possible simulation mismatch on property <INIT> of instance <valid_lut> set by attribute.
    Set user-defined property "INIT =  0040" for instance <valid_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 254: Possible simulation mismatch on property <INIT> of instance <purge_lut> set by attribute.
    Set user-defined property "INIT =  54" for instance <purge_lut> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 284: Possible simulation mismatch on property <INIT> of instance <delay15_srl00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay15_srl00> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl1> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl2> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl3> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl4> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl5> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl6> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl7> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 306: Possible simulation mismatch on property <INIT> of instance <delay16_srl8> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay16_srl8> in unit <kcuart_rx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" line 331: Possible simulation mismatch on property <INIT> of instance <strobe_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <strobe_lut> in unit <kcuart_rx>.
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.

Analyzing Entity <ClockGen> (Architecture <behavioral>).
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 98: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 106: Generating a Black Box for component <BUFG>.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK90' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK270' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKDV' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLK2X180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'CLKFX180' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'STATUS' of component 'DCM'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Unconnected output port 'PSDONE' of component 'DCM'.
WARNING:Xst:766 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" line 110: Generating a Black Box for component <DCM>.
Entity <ClockGen> analyzed. Unit <ClockGen> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kcuart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd".
Unit <kcuart_rx> synthesized.


Synthesizing Unit <bbfifo_16x8>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd".
Unit <bbfifo_16x8> synthesized.


Synthesizing Unit <kcuart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd".
Unit <kcuart_tx> synthesized.


Synthesizing Unit <ClockGen>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd".
Unit <ClockGen> synthesized.


Synthesizing Unit <uart_rx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd".
Unit <uart_rx> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd".
Unit <uart_tx> synthesized.


Synthesizing Unit <uclock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD".
Unit <uclock> synthesized.


Synthesizing Unit <kcpsm3>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <uart_clock>.
    Related source file is "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd".
WARNING:Xst:646 - Signal <port_id<7:1>> is assigned but never used.
    Found 1-bit register for signal <alarm>.
    Found 7-bit up counter for signal <baud_count>.
    Found 1-bit register for signal <en_16_x_baud>.
    Found 8-bit register for signal <in_port>.
    Found 1-bit register for signal <interrupt>.
    Found 1-bit register for signal <read_from_uart>.
    Found 6-bit up counter for signal <timer_count>.
    Found 1-bit register for signal <timer_pulse>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <uart_clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 6-bit up counter                  : 1
 7-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 5
 8-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uart_clock> ...

Optimizing unit <kcuart_rx> ...

Optimizing unit <bbfifo_16x8> ...

Optimizing unit <kcpsm3> ...

Optimizing unit <kcuart_tx> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx/ISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart_clock, actual ratio is 8.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     198  out of   1920    10%  
 Number of Slice Flip Flops:           146  out of   3840     3%  
 Number of 4 input LUTs:               269  out of   3840     7%  
 Number of bonded IOBs:                  6  out of    173     3%  
 Number of BRAMs:                        1  out of     12     8%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                | Load  |
-----------------------------------+------------------------------------------------------+-------+
clk_in(IBUFG_clk:O)                | Clock55MHz/DCM_INST:CLKFX(*)(processor/logical_flop5)| 208   |
-----------------------------------+------------------------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.263ns (Maximum Frequency: 97.439MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\xup\markets\plds\workshops\courses\v71_fpga_flow\labs\work\vhdl\picoblaze_clo
ck/_ngo -nt timestamp -uc uart_clock.ucf -p xc3s200-ft256-4 uart_clock.ngc
uart_clock.ngd 

Reading NGO file
'C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Cl
ock/uart_clock.ngc' ...
WARNING:NgdBuild:889 - Pad net 'clk_in' is not connected to an external port in
   this design.  A new port 'clk_in' has been added and is connected to this
   signal.

Applying constraints in "uart_clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'clk_in' has multiple driver(s):
     pin O on block IBUFG_clk with type IBUFG,
     pin PAD on block clk_in with type PAD
ERROR:NgdBuild:924 - input pad net 'clk_in' is driving non-buffer primitives:
     pin O on block IBUFG_clk with type IBUFG

NGDBUILD Design Results Summary:
  Number of errors:     2
  Number of warnings:   1


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "uart_clock.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_rx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" in Library work.
Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" in Library work.
Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" in Library work.
Architecture low_level_definition of Entity uclock is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_tx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_tx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/uart_rx.vhd" in Library work.
Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/ClockGen.vhd" in Library work.
Architecture behavioral of Entity clockgen is up to date.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" in Library work.
Entity <uart_clock> compiled.
Entity <uart_clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart_clock> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 267: Mux is complete : default of case is discarded
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 357: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'ClockGen'.
WARNING:Xst:753 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/PicoBlaze_Clock/uart_clock.vhd" line 357: Unconnected output port 'CLK0_OUT' of component 'ClockGen'.
Entity <uart_clock> analyzed. Unit <uart_clock> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 503: Possible simulation mismatch on property <INIT> of instance <high_zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 525: Possible simulation mismatch on property <INIT> of instance <sel_shadow_zero_lut> set by attribute.
    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 554: Possible simulation mismatch on property <INIT> of instance <low_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 564: Possible simulation mismatch on property <INIT> of instance <high_parity_lut> set by attribute.
    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 587: Possible simulation mismatch on property <INIT> of instance <sel_parity_lut> set by attribute.
    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 597: Possible simulation mismatch on property <INIT> of instance <sel_arith_carry_lut> set by attribute.
    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 606: Possible simulation mismatch on property <INIT> of instance <sel_shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 614: Possible simulation mismatch on property <INIT> of instance <sel_shadow_carry_lut> set by attribute.
    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux8> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 682: Possible simulation mismatch on property <INIT> of instance <vector_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <vector_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 691: Possible simulation mismatch on property <INIT> of instance <value_select_mux9> set by attribute.
    Set user-defined property "INIT =  E4" for instance <value_select_mux9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 794: Possible simulation mismatch on property <INIT> of instance <register_type_lut> set by attribute.
    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 809: Possible simulation mismatch on property <INIT> of instance <register_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit00> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit00> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit10> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit10> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit20> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit20> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit30> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit30> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit40> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit40> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit50> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit50> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit60> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit60> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 828: Possible simulation mismatch on property <INIT> of instance <register_bit70> set by attribute.
    Set user-defined property "INIT =  0000" for instance <register_bit70> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 846: Possible simulation mismatch on property <INIT> of instance <operand_select_mux7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <operand_select_mux7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 871: Possible simulation mismatch on property <INIT> of instance <memory_type_lut> set by attribute.
    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 886: Possible simulation mismatch on property <INIT> of instance <memory_enable_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit0> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit1> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit2> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit3> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit4> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit5> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit6> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 906: Possible simulation mismatch on property <INIT> of instance <memory_bit7> set by attribute.
    Set user-defined property "INIT =  0000000000000000" for instance <memory_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 937: Possible simulation mismatch on property <INIT> of instance <sel_logical_lut> set by attribute.
    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut0> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut1> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut2> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut3> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut4> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut5> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut6> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 956: Possible simulation mismatch on property <INIT> of instance <logical_lut7> set by attribute.
    Set user-defined property "INIT =  6E8A" for instance <logical_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 989: Possible simulation mismatch on property <INIT> of instance <high_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 998: Possible simulation mismatch on property <INIT> of instance <low_shift_in_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1015: Possible simulation mismatch on property <INIT> of instance <shift_carry_lut> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1041: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1061: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1081: Possible simulation mismatch on property <INIT> of instance <shift_mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <shift_mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1109: Possible simulation mismatch on property <INIT> of instance <sel_arith_lut> set by attribute.
    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1136: Possible simulation mismatch on property <INIT> of instance <arith_carry_in_lut0> set by attribute.
    Set user-defined property "INIT =  6C" for instance <arith_carry_in_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut0> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut1> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut2> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut3> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut4> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut5> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut6> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1200: Possible simulation mismatch on property <INIT> of instance <arith_carry_out_lut7> set by attribute.
    Set user-defined property "INIT =  2" for instance <arith_carry_out_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1220: Possible simulation mismatch on property <INIT> of instance <arith_lut7> set by attribute.
    Set user-defined property "INIT =  96" for instance <arith_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1244: Possible simulation mismatch on property <INIT> of instance <input_fetch_type_lut> set by attribute.
    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut0> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut0> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut1> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut1> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut2> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut2> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut3> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut3> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut4> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut4> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut5> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut5> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut6> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut6> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1269: Possible simulation mismatch on property <INIT> of instance <or_lut7> set by attribute.
    Set user-defined property "INIT =  FE" for instance <or_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1278: Possible simulation mismatch on property <INIT> of instance <mux_lut7> set by attribute.
    Set user-defined property "INIT =  E4" for instance <mux_lut7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1301: Possible simulation mismatch on property <INIT> of instance <io_decode_lut> set by attribute.
    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1311: Possible simulation mismatch on property <INIT> of instance <write_active_lut> set by attribute.
    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1327: Possible simulation mismatch on property <INIT> of instance <read_active_lut> set by attribute.
    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit0> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit1> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit2> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit3> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit4> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit4> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit5> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit5> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit6> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit6> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit7> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit7> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit8> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit8> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1368: Possible simulation mismatch on property <INIT> of instance <stack_bit9> set by attribute.
    Set user-defined property "INIT =  00000000" for instance <stack_bit9> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1415: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6555" for instance <count_lut0> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut1> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut2> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1448: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut3> in unit <kcpsm3>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" line 1482: Possible simulation mismatch on property <INIT> of instance <count_lut4> set by attribute.
    Set user-defined property "INIT =  A999" for instance <count_lut4> in unit <kcpsm3>.
Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.

Analyzing Entity <uclock> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INITP_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_00> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_01> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_02> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_03> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_04> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_05> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_06> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_07> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_08> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_09> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_0F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_10> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_11> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_12> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_13> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_14> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_15> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_16> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_17> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_18> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_19> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_1F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_20> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_21> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_22> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_23> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_24> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_25> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_26> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_27> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_28> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_29> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_2F> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_30> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_31> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_32> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_33> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_34> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_35> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_36> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_37> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_38> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_39> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3A> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3B> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3C> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3D> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3E> of instance <ram_1024_x_18> set by attribute.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/UCLOCK.VHD" line 181: Possible simulation mismatch on property <INIT_3F> of instance <ram_1024_x_18> set by attribute.
    Set user-defined property "INIT_00 =  0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_01 =  40490091501200ED50374041501E40545012400D0091012000C30115C0010C00" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_02 =  5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_03 =  541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_04 =  5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_05 =  401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_06 =  1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_07 =  009181011420588B01EC548B403A009181011520588B01EC548B403A00918101" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_08 =  000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_09 =  50A220024000A000009D4F0140950185549A20104000A000810101E27010A000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0A =  013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0B =  4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0C =  810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0D =  400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0E =  0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_0F =  009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_10 =  009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_11 =  009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_12 =  0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_13 =  0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_14 =  009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_15 =  A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_16 =  F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_17 =  81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_18 =  EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_19 =  82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1A =  E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1B =  010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1C =  5010610A600755DB501061096006E106010041C9E10651C7411881016106E107" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1D =  6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1E =  1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_1F =  000000000000000000000000A0009200B80001E8701081010206920002060206" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INIT_3F =  43FC8001AC008D01000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_00 =  D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_01 =  CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_02 =  4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_03 =  0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
    Set user-defined property "INITP_07 =  F500000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <uclock>.
Entity <uclock> analyzed. Unit <uclock> generated.

Analyzing Entity <uart_tx> (Architecture <macro_level_definition>).
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing Entity <kcuart_tx> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 133: Possible simulation mismatch on property <INIT> of instance <mux1_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 143: Possible simulation mismatch on property <INIT> of instance <mux2_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 153: Possible simulation mismatch on property <INIT> of instance <mux3_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 163: Possible simulation mismatch on property <INIT> of instance <mux4_lut> set by attribute.
    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut0> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut1> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 221: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  8" for instance <count_lut2> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 270: Possible simulation mismatch on property <INIT> of instance <ready_lut> set by attribute.
    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 281: Possible simulation mismatch on property <INIT> of instance <start_lut> set by attribute.
    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 300: Possible simulation mismatch on property <INIT> of instance <run_lut> set by attribute.
    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 318: Possible simulation mismatch on property <INIT> of instance <hot_state_lut> set by attribute.
    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 333: Possible simulation mismatch on property <INIT> of instance <delay14_srl> set by attribute.
    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 354: Possible simulation mismatch on property <INIT> of instance <stop_lut> set by attribute.
    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcuart_tx.vhd" line 372: Possible simulation mismatch on property <INIT> of instance <complete_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.

Analyzing Entity <bbfifo_16x8> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl0> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl1> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl2> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl3> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl4> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl4> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl5> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl5> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl6> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl6> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 124: Possible simulation mismatch on property <INIT> of instance <data_srl7> set by attribute.
    Set user-defined property "INIT =  0000" for instance <data_srl7> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut0> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut0> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut1> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut1> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut2> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut2> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 158: Possible simulation mismatch on property <INIT> of instance <count_lut3> set by attribute.
    Set user-defined property "INIT =  6606" for instance <count_lut3> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 215: Possible simulation mismatch on property <INIT> of instance <zero_lut> set by attribute.
    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 226: Possible simulation mismatch on property <INIT> of instance <full_lut> set by attribute.
    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
WARNING:Xst:2185 - "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/bbfifo_16x8.vhd" line 239: Possible simu