Project Navigator Auto-Make Log File
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Started process "Check Syntax".

Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library isim_temp.
Entity <kcpsm3> compiled.
Entity <kcpsm3> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3_int_test.vhd" in Library isim_temp.
Entity <kcpsm3_int_test> compiled.
Entity <kcpsm3_int_test> (Architecture <Behavioral>) compiled.
Parsing "kcpsm3_int_test_stx.prj": 0.86


Project Navigator Auto-Make Log File
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Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library work.
Entity <kcpsm3> compiled.
Entity <kcpsm3> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3_int_test.vhd" in Library work.
Entity <kcpsm3_int_test> compiled.
Entity <kcpsm3_int_test> (Architecture <Behavioral>) compiled.
Parsing "kcpsm3_int_test_beh.prj": 0.50
Codegen   UNISIM/VPKG: 2.79
Codegen   UNISIM/VCOMPONENTS: 0.33
Codegen   unisim/LUT1: 0.01
Codegen   unisim/FDR: 0.01
Codegen   unisim/FDS: 0.04
Codegen   unisim/LUT4: 0.00
Codegen   unisim/FD: 0.01
Codegen   unisim/FDE: 0.01
Codegen   unisim/LUT3: 0.00
Codegen   unisim/FDRE: 0.00
Codegen   unisim/LUT2: 0.01
Codegen   unisim/MUXCY: 0.01
Codegen   unisim/XORCY: 0.00
Codegen   unisim/INV: 0.01
Codegen   unisim/FDRSE: 0.01
Codegen   unisim/RAM16X1D: 0.01
Codegen   unisim/RAM64X1S: 0.06
Codegen   unisim/MUXF5: 0.01
Codegen   unisim/RAM32X1S: 0.02
Codegen   work/KCPSM3: 0.01
Codegen   unisim/LUT1/LUT1_V: 0.32
Codegen   unisim/FDR/FDR_V: 0.31
Codegen   unisim/FDS/FDS_V: 0.32
Codegen   unisim/LUT4/LUT4_V: 0.40
Codegen   unisim/FD/FD_V: 0.30
Codegen   unisim/FDE/FDE_V: 0.32
Codegen   unisim/LUT3/LUT3_V: 0.37
Codegen   unisim/FDRE/FDRE_V: 0.30
Codegen   unisim/LUT2/LUT2_V: 0.36
Codegen   unisim/MUXCY/MUXCY_V: 0.29
Codegen   unisim/XORCY/XORCY_V: 0.26
Codegen   unisim/INV/INV_V: 0.27
Codegen   unisim/FDRSE/FDRSE_V: 0.36
Codegen   unisim/RAM16X1D/RAM16X1D_V: 0.47
Codegen   unisim/RAM64X1S/RAM64X1S_V: 0.47
Codegen   unisim/MUXF5/MUXF5_V: 0.30
Codegen   unisim/RAM32X1S/RAM32X1S_V: 0.47
Codegen   work/KCPSM3/LOW_LEVEL_DEFINITION: 2.48
Codegen   work/KCPSM3_INT_TEST: 0.00
Codegen   work/KCPSM3_INT_TEST/BEHAVIORAL: 0.40
Building kcpsm3_int_test_isim_beh.exe


Project Navigator Auto-Make Log File
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Started process "Check Syntax".

Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/test_bench.vhd" in Library isim_temp.
Entity <testbench> compiled.
Entity <testbench> (Architecture <behavior>) compiled.
Parsing "testbench_stx.prj": 0.34


Project Navigator Auto-Make Log File
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Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/test_bench.vhd" in Library work.
Entity <testbench> compiled.
Entity <testbench> (Architecture <behavior>) compiled.
Parsing "testbench_beh.prj": 0.24
Codegen   work/TESTBENCH: 0.01
Codegen   work/TESTBENCH/BEHAVIOR: 0.34
Building testbench_isim_beh.exe


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Check Syntax".

Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3.vhd" in Library isim_temp.
Entity <kcpsm3> compiled.
Entity <kcpsm3> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/INT_TEST.VHD" in Library isim_temp.
Entity <int_test> compiled.
Entity <int_test> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3_int_test.vhd" in Library isim_temp.
Entity <kcpsm3_int_test> compiled.
Entity <kcpsm3_int_test> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/test_bench.vhd" in Library isim_temp.
Entity <testbench> compiled.
Entity <testbench> (Architecture <behavior>) compiled.
Parsing "testbench_stx.prj": 0.57


Project Navigator Auto-Make Log File
-------------------------------------






Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/Assembler/INT_TEST.VHD" in Library work.
Entity <int_test> compiled.
Entity <int_test> (Architecture <low_level_definition>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/kcpsm3_int_test.vhd" in Library work.
Entity <kcpsm3_int_test> compiled.
Entity <kcpsm3_int_test> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/XUP/Markets/PLDs/Workshops/courses/v71_fpga_flow/labs/work/VHDL/test_bench.vhd" in Library work.
Entity <testbench> compiled.
Entity <testbench> (Architecture <behavior>) compiled.
Parsing "testbench_beh.prj": 0.45
Codegen   unisim/RAMB16_S18: 0.02
Codegen   work/INT_TEST: 0.01
Codegen   unisim/RAMB16_S18/RAMB16_S18_V: 1.45
Codegen   work/INT_TEST/LOW_LEVEL_DEFINITION: 0.51
Codegen   work/KCPSM3_INT_TEST: 0.01
Codegen   work/KCPSM3_INT_TEST/BEHAVIORAL: 0.40
Codegen   work/TESTBENCH: 0.01
Codegen   work/TESTBENCH/BEHAVIOR: 0.37
Building testbench_isim_beh.exe